(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a better controlled silicon nitride, Si3N4, spacer through a judicious ion implantation of nitride layer over the floating gate of a split-gate flash memory cell.
(2) Description of the Related Art
A spacer formed between the lower edges of the floating gate and the control gate of a split-gate flash memory cell will enhance the endurance (the number of times the cell can be written and erased) of the cell provided that the spacer is well defined, or shaped, and well formed. In current practice, the spacer is formed by overetching, which in turn makes it difficult to control the shape and size of the spacer as is described more in detail below. Consequently, the endurance is degraded as well as the erase and program (writing) speed of the cell. A poorly defined spacer will also cause, what is known in the art as xe2x80x9cwrite disturbxe2x80x9d, or, unwanted reverse tunneling, or erasing. It is disclosed in the embodiments of the present invention a method of forming reliable nitride spacers in split-gate flash memory cells.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIG. 1. There, a MOS transistor is formed on a semiconductor substrate (10) having a first doped region (11), a second doped region (13), a channel region (15), a gate oxide (30), a floating gate (40), intergate dielectric layer (50) and control gate (60). Substrate (10) and channel region (15) have a first conductivity type, and the first (11) and second (13) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in FIG. 1, the first doped region, (11), lies within the substrate. The second doped region, (13), lies within substrate (10) and is spaced apart form the first doped region (11). Channel region (15) lies within substrate (10) and between first (11) and second (13) doped regions. Gate oxide layer (30) overlies substrate (10). Floating gate (40), to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (30) while control gate (60), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (50) therebetween.
In the structure shown in FIG. 1, control gate (60) overlaps the channel region, (17), adjacent to channel (15) under the floating gate, (40). It will be known to those skilled in the art that this structure is needed because when the cell is erased, it leaves a positive charge on the floating gate. As a result, the channel under the floating gate becomes inverted. The series MOS transistor (formed by the control gate over the channel region) is needed in order to prevent current flow from control gate to floating gate. The length of the transistor, that is the overlap of the control gate over the channel region (17) determines the cell performance.
To program the transistor shown in FIG. 1 which shows the placement of gate, source and drain voltages or Vg, Vs and Vd, respectively, charge is transferred from substrate (10) through gate oxide (30) and is stored on floating gate (40) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed xe2x80x9conxe2x80x9d or xe2x80x9coff.xe2x80x9d xe2x80x9cReadingxe2x80x9d of the cell""s state is accomplished by applying appropriate voltages to the cell source (11) and drain (13), and to control gate (60), and then sensing the amount of charge on floating gate (40). To erase the contents of the cell, the programming process is reversed, namely, charges are removed from the floating gate by transferring them back to the substrate through the gate oxide. Electron tunneling occurs through oxide regions (33) and (53) shown in FIG. 1.
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (F-N) tunneling as is well known in prior art. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of Fowler-Nordheim tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, the floating gate can be erased by grounding the control gate and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate. Of importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Inadvertent reverse tunneling, or erasure, for example, may occur if the tunnel oxide is degraded, or the spacer formed between the floating gate and the control gate is poorly shaped.
In prior art, spacers are employed for various purposes. Wang in U.S. Pat. Nos. 5,811,853 and 5,597,751 forms a thick spacer oxide layer on top of a floating gate and the source/drain region of a substrate to prevent shorting thereinbetween in a memory cell. In U.S. Pat. No. 5,789,296, Sung teaches a method of forming a split-gate flash memory by preparing a substrate having an oxide layer; forming a first conduction layer over the oxide layer; etching a portion of the first conducting layer to form a word line structure for the flash memory; forming a spacer layer over the word line structure to be a side-wall portion of a word-line protecting layer; oxidizing the word-line protecting layer to form a dielectric layer, and forming a floating gate layer over the dielectric layer.
In another approach, Liang, et al., in U.S. Pat. No. 5,714,412 disclose a multi-level, split-gate flash memory cell where the memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covering turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlying the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes.
It is disclosed in the present invention a different method of forming a spacer in a split-gate flash memory cell by judiciously implanting the layer from which the spacer is formed.
It is therefore an object of this invention to provide method of forming a split-gate flash memory cell having a well shaped and well formed spacer between the lower edges of the floating gate and the control gate of the cell.
It is another object of this invention to provide a method of forming a nitride spacer through a judicious ion implanting of the nitride layer from which it is formed.
It is still another object of the present invention to provide split-gate flash memory cell having a rectangular shaped spacer between the lower edges of the floating gate and the control gate of the cell.
These objects are accomplished by providing a silicon substrate having a plurality of active and field regions defined; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide forming a first polysilicon layer over said gate oxide layer; forming a nitride layer over said first polysilicon layer; forming and patterning a first photoresist layer over said first polysilicon layer to form a photoresist mask with a pattern corresponding to the floating gate of said split-gate flash memory cell; etching said nitride layer through said photoresist mask to form an opening to expose a portion of the underlying said first polysilicon layer; removing said first photoresist layer; oxidizing said fist polysilicon layer exposed in said opening thus forming poly oxide over said first polysilicon layer; removing said nitride layer; using said poly oxide as a hard mask, etching said first polysilicon layer to form floating gate; forming high temperature oxide (HTO) layer over said substrate including said floating gate; forming silicon nitride layer over said HTO layer; vertical implanting said silicon nitride layer covering said substrate; performing a high selectivity etch of said silicon nitride layer to form silicon nitride spacer; forming an intergate oxide layer over said substrate; forming a second polysilicon layer over said intergate oxide layer; and patterning said second polysilicon layer with a second photoresist mask having control gate pattern to form a control gate to complete the forming of said split-gate flash memory cell.
These objects are further accomplished by providing a split-gate flash memory cell having a floating gate with vertical walls and a rectangular nitride spacer between the lower edges of the floating gate and the control gate of the memory cell.